The fabrication of a memory device typically requires a number of steps including lithography, deposition of various constituent materials, patterning, etching, etc. However, the continual reduction in the size of individual memory elements, and the continual increase in the density with which such memory elements are fabricated on memory devices, are challenging the limits of current lithography and patterning technology. For example, existing lithography and patterning technology is typically not well suited for forming features having a pitch less than about 32 nanometers. Available techniques are relatively expensive and require expensive processes such as immersion lithography, extreme-ultraviolet lithography (EUVL), and/or electron beam (e-beam) direct writing lithography. Accordingly, improved and more cost effective methods of patterning memory cells for use in memory devices are desirable. In particular, methods and apparatus for forming memory elements having small pitch, are desirable.